1. Field of the Invention
The invention relates to memory devices and, more particularly, to memory devices having a reduced number of wires for test mode signals.
2. Description of the Prior Art
Typically, various test mode signals are generated for testing the integrity of individual circuits of a memory device during initialization or after resetting of the device. The test mode signals are generated by a test mode (TM) block, wherein a memory device may have a single or many TM blocks. Regardless of the number of TM blocks, these blocks are usually situated near the centre of the chip, thereby enabling the test mode signals to be easily routed to all circuits on the device. As the number of circuits within a memory device increases, the routing becomes more complex. Moreover, it further complicates the routing issue with the reduction in size of a semiconductor device.